Metal-oxide semiconductor (hereinafter “MOS”) transistors fabricated on silicon-on-insulator (hereinafter “SOI”) wafers have received great attention because of advantages in device isolation, speed, density, and scalability over bulk silicon devices [1]. Although SOI devices are naturally resistant to transient photocurrents and single event upset, total-dose irradiation may induce a parasitic conduction path at the buried oxide (hereinafter “BOX”) interface due to radiation-induced oxide and interface traps [2]. On the other hand, it has been noted that with ever decreasing SOI thickness for future generation of the complementary metal-oxide semiconductor (hereinafter “CMOS”) technology, there will be a negative impact on carrier mobility in the channel because of the proximity of the Si/BOX interface to the gate (commonly SiO2). In addition, dopants may penetrate from the heavily doped polysilicon gate into the substrate, which causes instability in the threshold voltage. The performance and reliability of MOS structures depends more and more on the microscopic quality of dielectrics and their interfaces. Thus, characterization of these interfaces will be of increasing importance. Conventionally, the properties of the buried layer and interfaces of the SOI wafers have been investigated by means of destructive, non-real-time methods with limited sampling frequency, such as electrical characterization including current-voltage (hereinafter “I-V”) and capacitance-voltage (hereinafter “C-V”) measurements on patterned capacitor structures, point contact transistor measurements, and mercury probe measurements, etc., or physical measurements including atomic force microscopy following selective chemical etching. Wafer-level measurements via the pseudo-MOS technique are frequently used for evaluation of partially-processed wafers [3–5].
One of drawbacks of these destructive, non-real-time methods is that it damages the active device regions by directly probing the Si-film of the device, and it is limited to characterization of the top Si/SiO2 interface of the device.
Therefore, a heretofore unaddressed need still exists in the art to address the aforementioned deficiencies and inadequacies.